Minimum qualifications:

+ Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

+ 8 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.

+ 6 years of experience with IP Development or Integration.

+ Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques.

+ Experience with a scripting language like Perl or Python.

Preferred qualifications:

+ Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science.

+ Experience with ASIC design methodologies for clock domain checks, reset checks and low power design.

+ Experience with FPGA and emulation platforms.

+ Experience with high performance and energy efficient design techniques.

+ Experience with ASIC Verification or DFT.

+ Knowledge in Processor Cores, Buses/Fabric/NoC, Debug/Trace, Interrupts, or Clocks/Reset.

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

The US base salary range for this full-time position is $177,000-$266,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google (https://careers.google.com/benefits/) .

+ Manage micro-architecture definition for a subsystem/ASIC.

+ Perform integration of internal or external IP.

+ Perform RTL coding, function/performance simulation debug and Lint/CDC/FV/UPF checks.

+ Participate in synthesis, timing/power closure and FPGA/silicon bring-up.

+ Participate in test plan and coverage analysis of the sub-system and chip-level verification.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also https://careers.google.com/eeo/ and https://careers.google.com/jobs/dist/legal/OFCCP_EEO_Post.pdf If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form: https://goo.gl/forms/aBt6Pu71i1kzpLHe2.